Cirrus Logic CDB8422 - Manual (Page 18)

18 DS692DB2
CDB8422
2.5.2.3 AUX MCLK Source (AUX_Mclk)
Default = 0
Function:
This bit controls the source of the auxiliary MCLK signal. If the CS8422’s GPO3 pin is selected, the GPO3
pin should be configured to output XTI_OUT (CS8422 register 06h = XFh).
2.5.2.4 CS8422 Reset Pin (DUT_RST)
Default = 1
Function:
This bit controls the state of the CS8422’s RST pin.
2.5.3 Subclock Control (Address 03h)
2.5.3.1 TDM Header Subclock Source (TDM_SEL)
Default = 0
Function:
This bit controls the source of the LRCK and SCLK signals sent to the TDM header J30.
2.5.3.2 SAI Subclock Source (SAI_MS)
Default = 00
Function:
These bits control the direction of the LRCK and SCLK signals between the SAI header J22 and the
CS8422. The CS8422’ SAI port should be configured in the appropriate master/slave mode.
AUX_Mclk Setting AUX MCLK Source
0 ..........................................Y4 Canned Oscillator.
1 ..........................................CS8422 pin 30 (GPO3).
DUT_RST Setting CS8422 Reset State
0 ..........................................CS8422 in reset.
1 ..........................................CS8422 out of reset.
7 6 5 4 3 2 1 0
TDM_SEL Reserved SAI_MS1 SAI_MS0 SAO2_MS1 SAO2_MS0 SAO1_MS1 SAO1_MS0
TDM_SEL Setting TDM HDR Subclock Source
0 ..........................................CS8422 OLRCK2/OSCLK2.
1 ..........................................CS8422 OLRCK1/OSCLK1.
SAI_MS Setting SAI Subclock Source
00 ........................................HDR J22 drives CS8422’s ILRCK and ISCLK inputs.
01 ........................................CS8422’s ILRCK and ISCLK outputs drive HDR J22.
10 ........................................Reserved.
11.........................................Reserved.