Cirrus Logic CDB8422 - Manual (Page 15)

DS692DB2 15
CDB8422
2.3.4 FPGA Controls Tab
The “FPGA Controls” tab provides high-level control of the on-board FPGA’s register settings. This tab
provides controls for MCLK and subclock routing between devices on the CDB8422. Controls for the
CS8406 S/PDIF transmitter are also provided. A description of each control group is outlined below.
MCLK Routing - Specifies MCLK source for both serial audio output port headers on the board.
Subclock Routing - Controls bidirectional buffers to determine subclock signal direction between the
CS8422 and serial I/O interface headers. Make sure the CS8422 is also configured to properly output sub-
clocks in master mode or receiver subclocks in slave mode for each serial port.
CS8422 Controls - The state of the CS8422 reset pin may be set.
CS8406 Controls - Controls CS8406 settings and reset pin state.
Reset FPGA - Returns the FPGA and CS8422 to their default setup.
Update FPGA - Reads all registers in the FPGA and reflects the current values in the GUI.
Figure 9. FPGA Controls Tab