Cirrus Logic CDB8422 - Manual (Page 10)

10 DS692DB2
CDB8422
2.2.4 TDM In to TDM Out
The CS8422’s TDM output performance can be tested by loading the “TDM In to TDM Out” quick setup
file provided with the software package. The script configures the digital clock and data signal routing on
the board as shown in
Figure 5 .
TDM audio input data is provided by the TDM input header J30. The LRCK and SCLK signals located at
header J30 should be used to clock in the input TDM data. Optionally, digital S/PDIF input can be provided
on the optical (J1) or RCA (J7) jacks. Jumper J4 selects which input signal is connected to the RX0 pin of
the CS8422. The script configures the CS8422’s internal circuitry to multiplex the TDM input and S/PDIF
input data together and send the output data to serial output port 1. This data is presented as TDM audio
at header J24. The S/PDIF input data is also passed through (not multiplexed) to serial output port 2. This
data is presented as PCM audio at header J25. Refer to
Section 2.3 for details on software configuration.
Figure 5. TDM In to TDM Out
CS8422
Optical
S/PDIF In
J1
OR
RX0
Buffer
Header
J24
Buffer
Header
J25
(MASTER)
(MASTER)
J7
J4
Coaxial
S/PDIF In
OSCLK1
OLRCK1
SDOUT1
OSCLK2
OLRCK2
SDOUT2
OSCLK2
OLRCK2
SDOUT2
OSCLK1
OLRCK1
SDOUT1
XTI
J23
Y1
Header
J30
TDM
OSCLK
TDM
OLRCK
TDM IN
Buffer
TDM
Out
TDM_IN
TDM
In
PCM Out
no SRC
RMCK
MCLK OUT
MCLK OUT
GPO3
(XTI)