Cirrus Logic CDB8422 - Manual (Page 2)

2 DS692DB2
CDB8422
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4
1.1 Power ............................................................................................................................................... 4
1.2 Grounding and Power Supply Decoupling ....................................................................................... 4
1.3 FPGA ............................................................................................................................................... 4
1.4 CS8422 ............................................................................................................................................ 4
1.5 CS8406 Digital Audio Transmitter .................................................................................................... 5
1.6 CS8422 XTI Sources ....................................................................................................................... 5
1.7 I/O Stake Headers ........................................................................................................................... 5
1.8 S/PDIF and AES3/EBU Inputs ......................................................................................................... 5
2. SOFTWARE MODE ................................................................................................................................ 6
2.1 Quick Start Guide ............................................................................................................................. 6
2.2 Configuration Options ...................................................................................................................... 7
2.2.1 S/PDIF In to S/PDIF and PCM Out ......................................................................................... 7
2.2.2 AES3/EBU In to S/PDIF and PCM Out ................................................................................... 8
2.2.3 PCM In to S/PDIF and PCM Out ............................................................................................. 9
2.2.4 TDM In to TDM Out ............................................................................................................... 10
2.3 Software Mode Control .................................................................................................................. 11
2.3.1 CS8422 Main Setup Tab ....................................................................................................... 12
2.3.2 CS8422 Receiver Controls and Status Tab .......................................................................... 13
2.3.3 CS8422 Interrupt Controls and Status Tab ........................................................................... 14
2.3.4 FPGA Controls Tab ............................................................................................................... 15
2.3.5 Register Maps Tab ................................................................................................................ 16
2.4 FPGA Register Quick Reference ................................................................................................... 17
2.5 FPGA Register Descriptions .......................................................................................................... 17
2.5.1 Code Revision ID (Address 01h) - Read Only ....................................................................... 17
2.5.2 MCLK Control (Address 02h) ................................................................................................ 17
2.5.2.1 SAO2 HDR MCLK Source (SAO2_Mclk) ................................................................... 17
2.5.2.2 SAO1 HDR and CS8406 MCLK Source (SAO1_Mclk) .............................................. 17
2.5.2.3 AUX MCLK Source (AUX_Mclk) ................................................................................ 18
2.5.2.4 CS8422 Reset Pin (DUT_RST) ................................................................................. 18
2.5.3 Subclock Control (Address 03h) ............................................................................................ 18
2.5.3.1 TDM Header Subclock Source (TDM_SEL) .............................................................. 18
2.5.3.2 SAI Subclock Source (SAI_MS) ................................................................................ 18
2.5.3.3 SAO2 Subclock Source (SAO2_MS) ......................................................................... 19
2.5.3.4 SAO1 Subclock Source (SAO1_MS) ......................................................................... 19
2.5.4 CS8406 Control 1 (Address 04h) .......................................................................................... 19
2.5.4.1 OMCK/ILRCK Ratio (HWCK) ..................................................................................... 19
2.5.4.2 Validity Bit (VBIT_IN) ................................................................................................. 19
2.5.4.3 User Data (UBIT_IN) ................................................................................................. 20
2.5.4.4 TCBL (TCBL) ............................................................................................................. 20
2.5.4.5 C BIT (CBIT_INT) ...................................................................................................... 20
2.5.4.6 Interface Format (SFMT) ........................................................................................... 20
2.5.5 CS8406 Control 2 (Address 05h) .......................................................................................... 21
2.5.5.1 CS8406 Reset Pin (8406_RST) ................................................................................. 21
2.5.5.2 AUDIO Bit (AUDIOb) ................................................................................................. 21
3. HARDWARE MODE ............................................................................................................................. 22
3.1 Quick Start Guide ........................................................................................................................... 22
3.2 Configuration Options .................................................................................................................... 23
3.2.1 AES3/EBU In to S/PDIF and PCM Out ................................................................................. 23
3.2.2 TDM In to TDM Out ............................................................................................................... 24
3.3 Hardware Mode Control ................................................................................................................. 25
4. SYSTEM CONNECTIONS ................................................................................................................... 28