Cirrus Logic CDB8422 - Manual (Page 19)

DS692DB2 19
CDB8422
2.5.3.3 SAO2 Subclock Source (SAO2_MS)
Default = 00
Function:
These bits control the direction of the LRCK and SCLK signals between the SAO2 header J25 and the
CS8422. The CS8422’ SAO2 port should be configured in the appropriate master/slave mode.
2.5.3.4 SAO1 Subclock Source (SAO1_MS)
Default = 00
Function:
These bits control the direction of the LRCK and SCLK signals between the SAO1 header J24, the
CS8422, and the CS8406. The CS8406 will automatically switch between master and slave modes. The
CS8422’s SAO1 port should be configured in the appropriate master/slave mode.
2.5.4 CS8406 Control 1 (Address 04h)
2.5.4.1 OMCK/ILRCK Ratio (HWCK)
Default = 00
Function:
These bits control the ratio between the CS8406’s OMCK and ILRCK signals.
2.5.4.2 Validity Bit (VBIT_IN)
Default = 0
Function:
This bit controls the state of the validity bit for the CS8406’s output S/PDIF data.
SAO2_MS Setting SAO2 Subclock Source
00 ........................................HDR J25 drives CS8422’s OLRCK2 and OSCLK2 inputs.
01 ........................................CS8422’s OLRCK2 and OSCLK2 outputs drive HDR J25.
10 ........................................Reserved.
11.........................................Reserved.
SAO1_MS Setting SAO1 Subclock Source
00 ........................................HDR J24 drives CS8422’s OLRCK1 and OSCLK1 inputs and CS8406’s ILRCK and ISCLK inputs.
01 ........................................CS8406’s ILRCK and ISCLK outputs drive HDR J24 and CS8422’s OLRCK1 and OSCLK1 inputs.
10 ........................................CS8422’s OLRCK1 and OSCLK1 outputs drive HDR J24 and CS8406’s ILRCK and ISCLK inputs.
11.........................................Reserved.
7 6 5 4 3 2 1 0
HWCK1 HWCK0 VBIT_IN UBIT_IN TCBL CBIT_INT SFMT1 SFMT0
HWCK Setting OMCK/ILRCK Ratio
00 ........................................ILRCK = OMCK/256.
01 ........................................ILRCK = OMCK/128.
10 ........................................ILRCK = OMCK/512.
11.........................................Reserved.
VBIT_IN Setting Validity Polarity
0 ..........................................Low.
1 ..........................................High.
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