Cirrus Logic CDB42448 - Manual (Page 9)

CDB42448
DS648DB2 9
3. FPGA SYSTEM OVERVIEW
The FPGA (U14) controls all digital signal routing between the CS42448, CS8406 CS8416,
CS5341 and the DSP I/O Header. For easy evaluation of the TDM interface format of the
CS42448, the FPGA will copy stereo PCM data from either the CS8416 or DSP I/O Header onto
one data line at a 256Fs data rate. It will in turn de-multiplex the TDM data from the CS42448
and output stereo channel pairs to the CS8406.
3.1 FPGA Setup
Sections 3.2 to 3.4 show graphical descriptions of the routing topology internal to the FPGA.
Section 3.5 shows the graphical description of the FPGA’s control of the MCLK bus. And sec-
tion 3.6 provides details for routing clocks and data, bypassing the FPGA (recommended for
more advanced users only). Refer to “FPGA Register Description” on page 16 for all config-
uration settings.
The board may also be configured simply by choosing from 6 pre-defined scripts provided in
the supplied CD ROM. The pre-defined scripts, along with a brief description, are shown be-
low.
3.1.1 S/PDIF In, S/PDIF Out (SPDIF1-4)
This script sets up the CDB42448 to operate the CS8416 as the master and all other de-
vices as slave. The CS8416 masters the MCLK bus.
Various permutations of this option exist as S/PDIF1, S/PDIF2, S/PDIF3 and S/PDIF4.
Each permutation signifies which ADC data is transmitted to the CS8406.
The CS42448 operates in the TDM digital interface format. The FPGA copies PCM data
from the CS8416 onto one data line and transmits this data to the DAC_SDIN1 input.
3.1.2 Analog In, Analog Out (Digital Loopback)
This script sets up the CDB42448 to operate the crystal oscillator as the master. The
CS8416 passes the signal from the crystal oscillator, Y1, through its OMCK input and out
its RMCK output (NOTE: the S/PDIF input must be disconnected). The CS8416 then gen-
erates sub clocks derived from the crystal oscillator and input to the FPGA for TDM clock
generation. The FPGA then masters the sub clocks to the CS42448.
The CS42448 operates in the TDM digital interface format, looping ADC_SDOUT1 back
into the DAC_SDIN1 input. ADC1-3 appear on DAC1-3 and the CS5341 ADC appears on
DAC4.
3.1.3 DSP Routing
This script sets up the CDB42448 to operate the device attached to the DSP Header as
the master and all other devices as slave. The DSP Header masters the MCLK bus.