Cirrus Logic CDB42448 - Manual (Page 24)

CDB42448
24 DS648DB2
This bit toggles a control line for the external clock buffer to route the DSP clocks directly to the ADC
serial port (see Figure 7 on page 14).
5.7 DSP HEADER CONTROL (ADDRESS 07H)
5.7.1 DATA MUX(DATA_MUX[2:0])
Default = 000
Function:
This MUX selects the data lines from the ADC’s and the external ADC. The first selection shown in
Table 8 comes directly from data output lines. The last 7 are de-multiplexed from the TDM data stream
(NOTE: in this latter scenario, the data will need to be re-timed from the TDMer’s sub clocks). Refer
to Figure 4 on page 11.
5.7.2 FPGA TO DSP_DAC CLOCKS (FPGA->DSPDAC)
Default = 0
0 - FPGA Masters DSP_DAC clock bus
1 - FPGA Slave to DSP_DAC clock bus
Function:
This bit toggles a control line for the internal and external clock buffers for the DSP DAC headers (see
Figure 3 on page 10).
5.7.3 FPGA TO DSP_ADC CLOCKS (FPGA->DSPADC)
Default = 1
0 - FPGA Masters DSP_ADC clock bus
1 - FPGA Slave to DSP_ADC clock bus
Function:
This bit toggles a control line for the external clock buffer for the DSP ADC headers (see Figure 3 on
7 6 5 4 3 2 1 0
Reserved Reserved DATA_MUX2 DATA_MUX1 DATA_MUX0 FPGA->DSPDAC FPGA->DSPADC MCLK_M/S
DSP Data Selection
MUX[2:0] DSP.SDIN1 DSP.SDIN2 DSP.SDIN3
000 SDOUT1 SDOUT2 SDOUT3
001 ADC1 (from SDOUT1) ADC2 (from SDOUT1) ADC3 (from SDOUT1)
010 ADC2 (from SDOUT1) ADC3 (from SDOUT1) EXT_ADC (from SDOUT1)
011 ADC3 (from SDOUT1) EXT_ADC (from SDOUT1) ADC1 (from SDOUT1)
100 EXT_ADC (from SDOUT1) ADC1 (from SDOUT1) ADC2 (from SDOUT1)
101 ADC1 (from SDOUT1) ADC1 (from SDOUT1) ADC1 (from SDOUT1)
110 ADC2 (from SDOUT1) ADC2 (from SDOUT1) ADC2 (from SDOUT1)
111 ADC3 (from SDOUT1) ADC3 (from SDOUT1) ADC3 (from SDOUT1)
Table 8. Data to DSP