Cirrus Logic CDB42448 - Manual (Page 13)

CDB42448
DS648DB2 13
3.5 External MCLK Control
Several sources for MCLK exist on the CDB42448. The crystal oscillator, Y1, will master the
MCLK bus when no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for
details on OMCK operation). This signal will be driven directly out the CS8416.
The CS8416 will generate a master clock whenever its internal PLL is locked to the incoming
S/PDIF stream. This MCLK signal from the CS8416 can be taken off the MCLK bus by setting
the “RMCK_Master” bit in the register “CS8416 Control (address 05h)” on page 21.
The DSP Header can master or slave the MCLK bus by setting the “MCLK_M/S” bit in the
register “DSP Header Control (address 07h)” on page 24 accordingly.
3.5.1 CS5341 MCLK
To accommodate an MCLK signal greater than 25 MHz on the MCLK bus, a 2.0 divider
internal to the FPGA has been implemented. The divided MCLK signal is routed only to
the CS5341. Refer to register “CS5341 and Miscellaneous Control (Address 08h)” on
page 26 for the required setting.
3.5.2 TDMer MCLK
MCLK signals greater than 256Fs must be divided accordingly to maintain a 256Fs MCLK
signal into the TDMer. A 1.5 and a 2.0 divider has been implemented inside the FPGA.
Refer to register “CS5341 and Miscellaneous Control (Address 08h)” on page 26 for the
required setting.
CS8416
CS8406
DSP Header
FPGA
RMCK
OMCK OSC
OMCK
MCLK
CS42448
MCLK
CS5341
MCLK Divider
Divider TDMer
Reg 08h[6:5]
Reg 08h[3:2]
MCLK_M/S
Reg 07h[0]
RMCK_Master
Reg 05h[0]
Figure 6. External MCLK Control