Cirrus Logic CDB42448 - Manual (Page 10)

CDB42448
10 DS648DB2
3.2. Internal Sub-Clock Routing
The graphical description below shows the internal clock routing topology between the CS42448,
CS8416, CS8406 and DSP Header. Refer to registers “CODEC Clock Control (address 03h)” on
page 18, “CS8406 Control (address 04h)” on page 19 and “CS8416 Control (address 05h)” on
page 21 for configuration settings.
CS8416
DSP Header
LRCK
CS8406
CS42448
ADC_LRCK
ADC_SCLK
DAC_LRCK
DAC_SCLK
AUX_LRCK
AUX_SCLK
SCLK
DSP.ADC_LRCK
DSP.ADC_SCLK
DSP.DAC_LRCK
DSP.DAC_SCLK
LRCK
SCLK
CS8416 SCLK
DSP.ADC_SCLK
DAC SCLK
256Fs SCLK
CS8416 LRCK
DSP.ADC_LRCK
DAC LRCK
FS
ADC.CLK_MUX[1:0]
DAC LRCK
AUX LRCK
DAC SCLK
AUX SCLK
CS8416 LRCK
CS8416 SCLK
CS8416 SCLK
DSP.DAC_SCLK
ADC SCLK
256Fs SCLK
DAC_MUX[1:0]
CS8416 LRCK
DSP.DAC_LRCK
ADC LRCK
FS
ADC LRCK
T2P LRCK
ADC SCLK
T2P SCLK
ADC SCLK
ADC LRCK
DSP.ADC_LRCK
DSP.ADC_SCLK
DSP.DAC_LRCK
DSP.DAC_SCLK
AUX LRCK
AUX SCLK
TDMer
M/S AUX/DAC
FPGA->ADC
ADC_MUX[1:0]
DAC LRCK
DAC SCLK
T2P/ADC
FS
256Fs
DAC.CLK_MUX[1:0]
FPGA->DAC FPGA->DAC
FPGA->ADC
FPGA->DSPDAC
FPGA->DSPADC
Figure 3. Internal Sub-Clock Routing