Cirrus Logic CDB42448 - Manual (Page 2)

CDB42448
2 DS648DB2
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 Power ................................................................................................................................. 4
1.2 Grounding and Power Supply Decoupling ......................................................................... 4
1.3 FPGA ................................................................................................................................. 4
1.4 CS42448 Audio CODEC .................................................................................................... 4
1.5 CS8406 Digital Audio Transmitter ...................................................................................... 4
1.6 CS8416 Digital Audio Receiver .......................................................................................... 5
1.7 CS5341 .............................................................................................................................. 5
1.8 Canned Oscillator .............................................................................................................. 5
1.9 External Control Headers ................................................................................................... 5
1.10 Analog Input ..................................................................................................................... 6
1.11 Analog Outputs ................................................................................................................ 6
1.12 Serial Control Port ............................................................................................................ 6
1.13 USB Control Port ............................................................................................................. 6
2. SOFTWARE MODE .................................................................................................................. 7
2.1 Advanced Register Debug Tab .......................................................................................... 7
3. FPGA SYSTEM OVERVIEW .................................................................................................... 9
3.1 FPGA Setup ....................................................................................................................... 9
3.1.1 S/PDIF In, S/PDIF Out (SPDIF1-4) ....................................................................... 9
3.1.2 Analog In, Analog Out (Digital Loopback) ............................................................. 9
3.1.3 DSP Routing ......................................................................................................... 9
3.2. Internal Sub-Clock Routing ............................................................................................. 10
3.3. Internal Data Routing ...................................................................................................... 11
3.4. Internal TDM Conversion, MUXing and Control (TDMer) ............................................... 12
3.5 External MCLK Control .................................................................................................... 13
3.5.1 CS5341 MCLK .................................................................................................... 13
3.5.2 TDMer MCLK ...................................................................................................... 13
3.6 Bypass Control - Advanced ............................................................................................. 14
4. FPGA REGISTER QUICK REFERENCE ............................................................................... 15
5. FPGA REGISTER DESCRIPTION ......................................................................................... 16
6. CDB CONNECTORS AND JUMPERS ................................................................................... 28
7. CDB BLOCK DIAGRAM ................................................................................................... 30
8. CDB SCHEMATICS ............................................................................................................. 31
9. CDB LAYOUT ..................................................................................................................... 41
10. REVISION HISTORY ............................................................................................................ 44