Cirrus Logic CDB42448 - Manual (Page 4)

CDB42448
4 DS648DB2
1. SYSTEM OVERVIEW
The CDB42448 evaluation board is an excellent means for evaluating the CS42448 CODEC. An-
alog and digital audio signal interfaces are provided, an FPGA used for easily configuring the
board and a 9-pin serial cable for use with the supplied Windows
®
configuration software.
The CDB42448 schematic set has been partitioned into 10 pages and is shown in Figures 9
through 18.
1.1 Power
Power must be supplied to the evaluation board through the +5.0 V, +12.0 V and -12.0 V
binding posts. Jumper J1 connects the VA supply to a fixed +5.0 V or +3.3 V supply. VD, VLS
and VLC are all hard-tied to +3.3 V. All voltage inputs must be referenced to the single black
binding post ground connector (Figure 18 on page 40).
WARNING: Please refer to the CS42448 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS42448 requires careful attention to power supply and grounding arrangements to op-
timize performance. Figure 9 on page 31 provides an overview of the connections to the
CS42448. Figure 19 on page 41 shows the component placement. Figure 20 on page 42
shows the top layout. Figure 21 on page 43 shows the bottom layout. The decoupling capac-
itors are located as close to the CS42448 as possible. Extensive use of ground plane fill in
the evaluation board yields large reductions in radiated noise.
1.3 FPGA
See “FPGA System Overview” on page 9 for a complete description of how the FPGA (Figure
10 on page 32) is used on the CDB42448.
1.4 CS42448 Audio CODEC
A complete description of the CS42448 (Figure 9 on page 31) is included in the CS42448
product data sheet.
The required configuration settings of the CS42448 are made in its control port registers, ac-
cessible through the “CS42448” tab of the Cirrus Logic FlexGUI software.
Clock and data source selections are made in the control port of the FPGA, accessible
through the “FPGA” tab of the Cirrus Logic FlexGUI software. Refer to registers “CODEC
SDINx Control (address 02h)” on page 17 and “CODEC Clock Control (address 03h)” on
page 18 for configuration settings.
1.5 CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter (Figure 11 on page 33) and a discussion
of the digital audio interface are included in the CS8406 data sheet.
The CS8406 converts the PCM data generated by the CS42448 to the standard S/PDIF data
stream. The CS8406 operates in slave mode, accepting either a 128Fs or 256Fs master