Cirrus Logic CDB42448 - Manual (Page 15)

CDB42448
DS648DB2 15
4. FPGA REGISTER QUICK REFERENCE
Function 7 6 5 4 3 2 1 0
01h TDM Conver-
sion
DSP/CS8416 OUT1/OUT2 OUT1/OUT3 OUT1/OUT4 Reserved Reserved Reserved PDN_TDMer
p 16 default
0 0 0 0 0 0 0 0
02h CODEC
SDINx Con-
trol
SDIN4.MUX1 SDIN4.MUX0 SDIN3.MUX1 SDIN3.MUX0 SDIN2.MUX1 SDIN2.MUX0 SDIN1.MUX1 SDIN1.MUX0
p 17 default 1 1 1 1 1 1 1 0
03h CODEC
Clock Control
Reserved Reserved DAC.CLK_
MUX1
DAC.CLK_
MUX0
FPGA->DAC ADC.CLK_
MUX1
ADC.CLK_
MUX0
FPGA->ADC
p 18 default
0 0 1 1 0 1 1 0
04h CS8406 Con-
trol
Reserved RST MUX2 MUX1 MUX0 128/256 Fs I²S/LJ T2P/ADC
p 19 default 0 1 1 0 0 0 0 1
05h CS8416 Con-
trol
Reserved Reserved AUX/DAC RST M/S 128/256 Fs I²S/LJ RMCK_Master
p 21 default 0 0 1 1 1 0 0 0
06h Bypass Con-
trol
Reserved DSPDATA
->DAC
SDOUT->DSP CS5341
->AUX
DAC->DSP ADC->DSP DSP->DAC DSP->ADC
p 22 default 1 1 1 0 1 1 1 1
07h DSP Header
Control
Reserved Reserved DATA_MUX2 DATA_MUX1 DATA_MUX0 FPGA->DAC FPGA->ADC MCLK_M/S
p 24 default 0 0 0 0 0 0 1 0
08h CS5341/Misc
Control
Reserved Reserved INT.MCLK_
DIV
OMCK/DIV_
1.5/2
‘41_MCLK_
DIV
‘41_DIV_
1.5/2
‘41_I²S/LJ ‘41_RST
p 26 default 0 1 0 0 0 0 0 1