Cirrus Logic CDB42448 - Manual (Page 21)

CDB42448
DS648DB2 21
5.5 CS8416 CONTROL (ADDRESS 05H)
5.5.1 AUX OR DAC CLOCK SELECTION (AUX/DAC)
Default = 1
0 - DAC Sub-Clocks to CS8416
1 - AUX Sub-Clocks to CS8416
Function:
Selects the clock source for the CS8416 when in slave mode (see Figure 3 on page 10).
5.5.2 RESET (RST)
Default = 1
0 - CS8416 held in reset
1 - CS8416 taken out of reset
Function:
This bit is used to reset the CS8416 and is held low for 300
µs upon FPGA initialization. It is also
pulled low for 300
µs whenever registers 05h[3:1] change.
5.5.3 MASTER/SLAVE SELECT (M/S)
Default = 1
0 - Slave
1 - Master
Function:
Selects master/slave mode for the CS8416 and configures the internal routing buffers. Pin 6 (RST bit)
is held low for 300
µs whenever this bit changes.
5.5.4 RMCK/LRCK RATIO SELECT (128/256 FS)
Default = 0
0 - 256 Fs
1 - 128 Fs
Function:
Selects the RMCK/LRCK ratio for the CS8416. Pin 6 (RST bit) is held low for 300
µs whenever this
bit changes.
7 6 5 4 3 2 1 0
Reserved Reserved AUX/DAC RST M/S 128/256 Fs I²S/LJ RMCK_Master