Cirrus Logic AN368 - Manual (Page 48)

AN368
48 AN368REV2
5. The first filtered output is compared against a programmable code value that corresponds to the desired
shutoff temperature set point Temp
Shutdown
and is set using bits SHUTDWN[3:0] in register Config58 at
Address 90. The shutdown temperature code is configured as an offset from the wakeup temperature
code; Temp
eOTP
< Temp
Wakeup
< Temp
Shutdown
. See Equation 79:
6. The ADC output code is filtered using a faster low-pass filter with a programmable time constant
configured using bits EOTP_FLP[2:0] in register Config55 at Address 87.
7. For overtemperature compensation, a second low-pass filter with a programmable time constant of two
minutes is configured using bits EOTP_SLP[2:0] in register Config55 at Address 87.
8. Configure bits RATE[1:0] in register Config44 at Address 76 to set a rate to decrease the second-stage
dim level once the measured 8-bit temperature value corresponding to the external NTC resistance
connected to pin eOTP exceeds the temperature threshold set by bits eOTP[4:0]. The rate at which the
12-bit dim level is decreased is set to any one of the following:
EOTP_FLP[2:0] Time Constant
0 No filter
1 233ms
2 466ms
3 933ms
4 1.866s
5 3.733s
6 Reserved
7 Reserved
Table 5. Time Constant for First Low-pass Filter
EOTP_SLP[2:0] Time Constant
0 3.75s
1 7.5s
2 10s
3 15s
4 20s
5 30s
6 1min
7 2min
Table 6. Time Constant for Second Low-pass Filter
RATE[1:0] Dim Rate
0 4 dims per temperature code above CODE
TEMPeOTP
1 8 dims per temperature code above CODE
TEMPeOTP
2 16 dims per temperature code above CODE
TEMPeOTP
3 32 dims per temperature code above CODE
TEMPeOTP
Table 7. Dims Per Temperature Code
CODE
TEMPShutdown
CODE
TEMPWakeup
SHUTDWN  + [3:0] 4   = [Eq. 79]