An368 – Cirrus Logic AN368 User Manual
Page 27
AN368
AN368REV2
27
d. Set T2 Offset Delays to Get Optimum Linear Performance
A delay is present between the time the primary current reaches zero and the transfer of actual power to the
load, as shown in Figure 9. Correct measurement of the actual T2 time is important for the regulation loop to
help reduce errors in output current across the dim range.
Time T2
CHx
is solved using Equation 52:
where,
T2
raw
= Time between the negative edge of GD and negative edge of ZCD
T
RES
= Resonant period
T2
CHxOFF
= Td1+Td2 = G
Td1 and is the commutation time
G = Programmable T2
CHx
compensation gain
Td1 = Time that voltage V
Drain
is charged from 0 to V
BST
Td2 = Time that voltage V
Drain
is charged from V
BST
to (V
BST
+N
V
MODEx
)
GD
V
Drain
V
AUX
V
ZCD
V
BST
ZCD Comparator
Output
0
0
0
0
0
0
t
t
t
t
t
t
I
PRI
I
OUT
T2
T2
raw
T2
RES
Td1
Td2
Figure 9. Operation Waveforms for a Flyback Converter
T2
CHx
T2
raw
T
RES
4
-------------
–
T2
CHxOFF
–
=
[Eq. 52]
T2
raw
T
RES
4
-------------
–
T
d1
–
Td2
+
=
T2
raw
T
RES
4
-------------
–
G T
d1
–
=