Cirrus Logic AN368 - Manual (Page 20)

AN368
20 AN368REV2
m. Recalculate R
Sense
The flyback primary current is controlled by comparing the voltage across R
Sense
at pin FBSENSE to an
internal threshold of 1.4V. To guarantee the rated LED current under worst-case conditions, when the LED
string has maximum voltage, the V
BST
is at its minimum point and R
Sense
is at its highest tolerance. Adjust
R
Sense
to obtain the nominal LED current using Equations 31 and 32.
Once the current sense resistor R
Sense
value is determined, the target output current CHxCUR for the channel
can be calculated using Equation 37:
where,
V
Sense
= Voltage across sense resistor
I
CHx
= Current thought LED string
The target output current CHxCUR corresponds to a 9-bit OTP value and is programmed by bit CH1CURMSB
in register Config8 at Address 40 plus bits CH1CUR[7:0] at Address 41 for channel 1 and bit CH2CURMSB in
register Config10 at Address 42 plus bits CH2CUR[7:0] at Address 43 for channel 2.
Step 4) Tune Second-stage Performance and Limiting Parameters
The CS1630 LED controller provides a number of configurable parameters for controlling features of the
second-stage control. These features include leading- and falling-edge blanking times, configurable
deglitching of comparator outputs, dithering, resonant period probing, and phase synchronization. The optimal
values for many of the OTP general parameters not concerned with specific output design parameters have
been determined experimentally to cover the broadest design approaches. Unless there is a reason to change
them, these parameters are best set at their default values.
a. PID Feedback Controller
The maximum coefficient for the second-stage PID integrator is configured using register PID at Address 45.
The recommended value for a flyback topology that should be programmed in the PID register is ‘00000010’.
Bits RSHIFT[3:0] in register Config8 at Address 40 set the number of right shifts performed on the second-
stage PID integrator value to generate a 10-bit threshold value for the peak control comparator. For peak
rectify mode, the threshold is calculated by a right shift of the integrator value. For example, setting
RSHIFT[3:0] to 12, the 24-bit integrator is shifted right 12 times, and the remaining bits represent the threshold
value provided to the peak control comparator. The recommended value that should be programmed in
RSHIFT[3:0] is ‘1100’.
b. Leading-edge Blanking
Configurable blanking time on the I
Sense
comparator provides protection to suppress potential false
comparator values caused by spurious noise induced by the power FET switching at the rising edge of the gate
drive. The controller ignores output from the comparator from the rising edge of the gate drive to the end of the
blanking time interval. The duration of the leading-edge blanking time T
LEB
is set using the LEB[3:0] bits in
register Config18 at Address 50.
A setting of LEB[3:0] = 2 results in a leading-edge blanking time of 200ns. In addition, the leading-edge
blanking sets the minimum gate drive duration or T1 time for the design. Since the I
Sense
comparator is ignored
during the leading-edge blanking time, the gate drive remains asserted throughout the leading-edge blanking
time.
CHxCUR
511 2 R
Sense
I
CHx
  
N V
Sense

------------------------------------------------------- = [Eq. 37]
[Eq. 38] T
LEB
LEB[3:0]  = 2  50ns  