HP 8.20q Fibre Channel Switch - Manual (Page 100)

100 Managing ports
I/O Stream Guard
The I/O Stream Guard feature suppresses the Registered State Change Notification (RSCN) messages on
a port basis. I/O Stream Guard should be enabled only on ports connected to initiator devices. To
configure the I/O Stream Guard option using the Port Properties dialog box, open the Port menu, and
select Port Properties. Select one of the following options:
• Enable—Suppresses the reception of RSCN messages from other ports for which I/O Stream Guard is
enabled.
• Disable—Allows free transmission and reception of RSCN messages.
• Auto—Suppresses the reception of RSCN messages when the port is connected to an initiator device
with an HBA. The default is Auto. See ” Device Scan ” on page 100.
Device Scan
The Device Scan feature queries the connected device during login for FC-4 descriptor information.
Disable this parameter only if the scan creates a conflict with the connected device.
Auto Performance Tuning and AL Fairness
The Auto Perf Tuning and AL Fairness settings are configured using the Advanced Port Properties dialog
box ( Figure 50 ). The Auto Perf Tuning option enables the switch to dynamically control the MFS_Enable,
VI_Enable and LCF_Enable features based on the operational state of the port. The AL Fairness option
controls how frequently the switch can arbitrate for access. Applies only to ports running in loop (FL) mode.
To open the Advanced Port Properties dialog box, select one or more ports, open the Port menu, and then
select Advanced Port Properties.
Figure 50 Advanced Port Properties dialog box
Resetting a port
The Reset Port option reinitializes the port using the saved configuration. To reset a port:
1. In the faceplate display, select the port(s) to be reset.
2. Select Port > Reset Port.
3. Click Yes to reset the selected port(s).
Testing ports
You can test a port using the Port Diagnostics dialog box. Only one port can be tested at a time for each
type of test. The Port Diagnostics dialog box ( Figure 51 ) presents the following tests:
• Internal is a disruptive test that verifies port circuitry. The SerDes level test sends a test frame from the
ASIC through the SerDes chip and back to the ASIC for the selected ports. The port passes the test if the