Rainbow Electronics MAX3942 - Manual (Page 7)

MAX3942
10Gbps Modulator Driver
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Detailed Description
The MAX3942 modulator driver accepts differential
clock and data inputs that are compatible with PECL
and CML logic levels.
The modulation output stage is composed of a high-
speed differential pair and a programmable current
source with a maximum modulation current of 120mA.
The rise and fall times are typically 23ps. The modulation
current is designed to produce a modulation voltage up
to 3.0V
P-P single endedly, or 6.0V P-P differentially when
driving a 50
Ω module. The 3.0V
P-P results from 120mA P-P
through the parallel combination of the 50 Ω modulator
load and the internal 50 Ω back termination.
Polarity Switch
The MAX3942 includes a polarity switch. When the
PLRT pin is high or left floating, the outputs maintain the
polarity of the input data. When the PLRT pin is low, the
outputs are inverted relative to the input data.
Clock/Data Input Logic Levels
The MAX3942 is directly compatible with ground-refer-
ence CML. Either DC- or AC-coupling may be used for
CML referenced to ground. For all other logic types,
AC-coupling should be used.
Optional Data Input Latch
To reject pattern-dependent jitter in the input data, a syn-
chronous differential clock signal should be connected to
the CLK+ and CLK- inputs, and the RTEN control input
should be connected to V
EE
.
PIN NAME FUNCTION
1 DATA+ Noninverting Data Input, with 50 Ω On-Chip Termination
2 DATA- Inverting Data Input, with 50 Ω On-Chip Termination
3, 4, 14, 17 GND Ground. All pins must be connected to board ground.
5 CLK+ Noninverting Clock Input for Data Retiming, with 50 Ω On-Chip Termination
6 CLK- Inverting Clock Input for Data Retiming, with 50 Ω On-Chip Termination
7, 11, 12, 13,
18, 19, 21, 24
V EE Negative Supply Voltage. All pins must be connected to board V EE .
8 PWC+ Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section).
9 PWC-
Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width
adjustment feature (see the Design Procedure section).
10 MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output.
15 OUT-
Inverting Driver Output. Provides modulation output with 50 Ω back termination. Sinks current when
PLRT is high and when differential data is high.
16 OUT+
Noninverting Driver Output. Provides modulation output with 50 Ω back termination. Sinks current
when PLRT is high and when differential data is low.
20 PLRT
Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the
differential signal polarity. Contains an internal 100k
Ω pullup to GND.
22 MODEN
TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM
in the absorption (logic 0) state. Contains an internal 100k
Ω pulldown to V
EE .
23 RTEN Data-Retiming Input. Connect to V EE for retimed data. Connect to GND to bypass retiming latch.
EP
Exposed
Pad
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance.
See the Layout Considerations section.
Pin Description