Rainbow Electronics DS2165Q - Manual (Page 11)

DS2165/DS2165Q
041295 11/17
TIME SLOT RESTRICTIONS
Under certain conditions, the DS2165 does contain
some restrictions on the output time slots that are avail-
able. These restrictions are covered in detail in a sepa-
rate application note. No restrictions occur if the
DS2165 is operated in the hardware mode.
INPUT TO OUTPUT DELAY
With all three compressions algorithms, the total delay,
from the time the PCM data sample is captured by the
DS2165 to the time it is output, is always less than 375
µ s. The exact delay is determined by the input and out-
put time slots selected for each channel.
CHANNEL ASSOCIATED SIGNALING
The DS2165 supports Channel Associated Signaling
(CAS) via its ability to automatically change from the
32Kbps compression algorithm to the 24Kbps algo-
rithm. If the DS2165 is configured to perform the 32Kbps
algorithm, then in both the hardware and software
mode, it will sense the frame sync inputs (FSX and FSY)
for a double wide frame sync pulse. Whenever the
DS2165 receives a double wide pulse, it will automati-
cally switch from the 32Kbps algorithm to the 24Kbps al-
gorithm. Switching to the 24Kbps algorithm allows the
user to insert signaling data into the LSB bit position of
the ADPCM output because this bit does not contain
any useful speech information.
ON-THE-FLY ALGORITHM SELECTION
In the software mode, the user can switch between the
three available algorithms on-the-fly. That is, the
DS2165 does not need to be reset or stopped to make
the change from one algorithm to another. The DS2165
reads the Control Register before it starts to process
each PCM or ADPCM sample. If the user wishes to
switch algorithms, then the Control Register must be up-
dated via the serial port before the first input sample to
be processed with the new algorithm arrives at either
XIN or YIN. The PCM and ACPCM outputs will tristate
during register updates.