Rainbow Electronics DS3184 - Manual (Page 9)

Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4
Rev 1.5 9 of 13 022304
• Automatic packet abort insertion
• Packet scrambling using the self-synchronizing scrambler (x
43 +1)
• Controls include enables/disables/settings for: packet processing, FCS insertion or overwrite, 16/32-
bit FCS, inter-frame fill type/length, scrambling, FCS error insertion type/rate/count
• Counters for number of packets and bytes read from the transmit FIFO
3.13 Transmit PLCP Formatter Features
• Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes
• Generation of BIP-8 (B1), FEBE and RAI (G1)
• C1 cycle/stuff counter generation referenced to the 8KREFI input pin, referenced to the received
PLCP timing, or based on a fixed stuff pattern
• Automatic or manual insertion of FAS errors, BIP-8 errors
• All path overhead fields can be sourced from the PLCP transmit overhead port
3.14 Transmit DS3/E3 Formatter Features
• Insertion of framing overhead for M23 or C-bit parity DS3, G.751 E3 or G.832 E3
• B3ZS/HDB3 encoding
• Generation of RDI, AIS, DS3 idle signal, and G.832-E3 RDI
• Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-
bit errors, M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end
block errors (FEBE)
• HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national
bit, or G.832 NR or GC channels
• FEAC controller for DS3 FEAC channel can be configured to send one codeword, one codeword
continuously, or two different codewords back-to-back to send DS3 Line Loopback commands
• 16-byte Trail Trace Buffer sources the G.832 trail access point identifier
• Insertion of G.832 payload type and timing marker bits from registers
• C bits configurable as payload or overhead; as overhead they can be controlled from registers or the
transmit overhead port
• Most framing overhead fields can be sourced from transmit overhead port
• Formatter pass-through mode for clear channel applications and externally defined frame formats
• Built-in support for subrate DS3/E3
3.15 Transmit DS3/E3 LIU Features
• Wide 50±20% transmit clock duty cycle
• Line Build-Out (LBO) control
• Tri-state line driver outputs support protection switching applications
• Per-channel power-down control
• Output driver monitor
3.16 HDLC Controller Features
• 256-byte receive and transmit FIFOs
• Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking,
abort generation/checking, flag generation/detection, and byte alignment
• Programmable high or low water marks for the transmit and receive FIFOs