Rainbow Electronics ATtiny2313 - Manual (Page 62)

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ATtiny2313
2543A–AVR–08/03
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 33. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
General Interrupt Mask
Register – GIMSK
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU Control Register – MCUCR – define whether the external interrupt is
activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT1 is configured as an output. The correspond-
ing interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU Control Register – MCUCR – define whether the external interrupt is
activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT0 is configured as an output. The correspond-
ing interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK
Register.
Table 33. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
Bit 7 6 5 4 3 2 1 0
INT1 INT0 PCIE – – – – – GIMSK
Read/Write R/W R/W R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0