Rainbow Electronics ATtiny2313 - Manual (Page 22)

22
ATtiny2313
2543A–AVR–08/03
System Clock and
Clock Options
Clock Systems and their
Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 30. The clock systems
are detailed below.
Figure 11. Clock Distribution
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Reg-
ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and
USART. The I/O clock is also used by the External Interrupt module, but note that some
external interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted. Also note that start condition detection in the USI
module is carried out asynchronously when clk
I/O
is halted, enabling USI start condition
detection in all sleep modes.
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
General I/O
Modules
CPU Core RAM
clk
I/O AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Crystal
Oscillator
External Clock