Rainbow Electronics ATtiny2313 - Manual (Page 33)

33
ATtiny2313
2543A–AVR–08/03
Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.
The most important is then to ensure that no pins drive resistive loads. In sleep modes
where the I/O clock (clk
I/O
) is stopped, the input buffers of the device will be disabled.
This ensures that no power is consumed by the input logic when not needed. In some
cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 51 for
details on which pins are enabled. If the input buffer is enabled and the input signal is
left floating or have an analog signal level close to V
CC
/2, the input buffer will use exces-
sive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to V
CC
/2 on an input pin can cause significant current even in active
mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-
ters (DIDR). Refer to “Digital Input Disable Register – DIDR” on page 152.