Rainbow Electronics ATtiny2313 - Manual (Page 40)

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ATtiny2313
2543A–AVR–08/03
Watchdog Timer The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted
as shown in Table 21 on page 42. The WDR – Watchdog Reset – instruction resets the
Watchdog Timer value to 0. The Watchdog Timer is also reset when it is disabled and
when a Chip Reset occurs. Ten different clock cycle periods can be selected to deter-
mine the reset period. If the reset period expires without another Watchdog Reset, the
ATtiny2313 resets and executes from the Reset Vector. For timing details on the Watch-
dog Reset, refer to Table 21 on page 42.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset.
This can be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out
period, two different safety levels are selected by the fuse WDTON as shown in Table
19. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer”
on page 44 for details.
Figure 20. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is
executed.
Table 19. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT Initial
State How to Disable the
WDT How to Change
Time-out
Unprogrammed 1 Disabled Timed sequence No limitations
Programmed 2 Enabled Always enabled Timed sequence
OSC/2K OSC/4K OSC/8K
OSC/16K OSC/32K OSC/64K
OSC/128K OSC/256K OSC/512K OSC/1024K
MCU RESET
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
Bit 7 6 5 4 3 2 1 0
WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 X 0 0 0