Rainbow Electronics ATtiny2313 - Manual (Page 61)

61
ATtiny2313
2543A–AVR–08/03
External Interrupts
The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT15..0
pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1or
PCINT15..0 pins are configured as outputs. This feature provides a way of generating a
software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8
pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.
The PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change
interrupts. Pin change interrupts on PCINT15..0 are detected asynchronously. This
implies that these interrupts can be used for waking the part also from sleep modes
other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level.
This is set up as indicated in the specification for the External Interrupt Control Register
A – EICRA. When the INT0 or INT1 interrupt is enabled and is configured as level trig-
gered, the interrupt will trigger as long as the pin is held low. Note that recognition of
falling or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock,
described in “Clock Systems and their Distribution” on page 22. Low level interrupt on
INT0 and INT1 is detected asynchronously. This implies that this interrupt can be used
for waking the part from sleep modes other than Idle mode. The I/O clock is halted in all
sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 22.
MCU Control Register –
MCUCR The External Interrupt Control Register A contains control bits for interrupt sense
control.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in Table 33. The value on the INT1 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Bit 7 6 5 4 3 2 1 0
PUD SM1 SE SMD ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 32. Interrupt 0 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any logical change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.