Rainbow Electronics RA01 - Manual (Page 18)

RA01
Version: 1.0 Date: 10/8/2008
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Wake-Up Timer Calibration
By default the wake-up timer is calibrated each time it is enabled by setting the et bit in the Configuration Setting
Command . After timeout the timer restarts automatically and can be stopped by resetting the et bit. If the timer is
programmed to run for longer periods, at app. every 30 seconds it performs additional self-calibration.
This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software
algorithm can then compensate for the gradual shift caused by temperature change.
Bit dcal in the Extended Features Command (page 15) controls the automatic calibration feature. It is reset to 0 at
power-on and the automatic calibration is enabled. This is necessary to compensate for process tolerances. After
one calibration cycle further (re)calibration can be disabled by setting this bit to 1.
RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these
errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX
and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of
accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference
frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference
frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have
identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the
receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In
order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control
Command (bit 0).
CRYSTAL SELECTION GUIDELINES
The crystal oscillator of the RA01 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load
capacitor in order to minimize the external component count. The internal load capacitance value is programmable
from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to
20 pF so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C
0
) value is
expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent
series loss resistance). However, lower C
0
and ESR values guarantee faster oscillator startup.
The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (f
LO
).
Therefore f
LO
is directly proportional to the crystal frequency. The accuracy requirements for production tolerance,
temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error.
Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate
frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required
load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by
its motional capacitance and C
0
.
The on chip AFC is capable to correct TX/RX carrier offsets as much as 80% of the deviation of the received OOK
modulated signal.
Note: There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by
standards and/or channel separations.