NEC uPD78P078 - Manual (Page 556)

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CHAPTER 25 RESET FUNCTION
Table 25-1. Hardware Status after Reset (2/3)
Hardware Status after Reset
8-bit timer/event counters Timer register (TM5, TM6) 00H
5 and 6 Compare register (CR50, CR60) 00H
Clock select register (TCL5, TCL6) 00H
Mode control register (TMC5, TMC6) 00H
Watch timer Mode control register (TMC2) 00H
Watchdog timer
Clock select register (TCL2) 00H
Mode register (WDTM) 00H
Serial interface Clock select register (TCL3) 88H
Shift registers (SIO0, SIO1) Undefined
Mode registers (CSIM0, CSIM1, CSIM2) 00H
Serial bus interface control register (SBIC) 00H
Slave address register (SVA) Undefined
Automatic data transmit/receive control 00H
register (ADTC)
Automatic data transmit/receive address 00H
pointer (ADTP)
Automatic data transmit/receive interval 00H
specify register (ADTI)
Asynchronous serial interface mode 00H
register (ASIM)
Asynchronous serial interface status 00H
register (ASIS)
Baud rate generator control register (BRGC) 00H
Transmit shift register (TXS) FFH
Receive buffer register (RXB)
Interrupt timing specify register (SINT) 00H
A/D converter Mode register (ADM) 01H
Conversion result register (ADCR) Undefined
Input select register (ADIS) 00H
D/A converter Mode register (DAM) 00H
Conversion value setting register 00H
(DACS0, DACS1)
Real-time output port Mode register (RTPM) 00H
Control register (RTPC) 00H
Buffer register (RTBL, RTBH) 00H
ROM correction Correction address register (CORAD0, CORAD1) 00H
Correction control register (CORCN) 00H