NEC uPD78P078 User Manual
Page 197
197
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
(7) Sampling clock select registers (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS value to 00H.
Figure 8-9. Sampling Clock Select Register Format
Caution f
XX
/2
N
is the clock supplied to the CPU, and f
XX
/2
5
, f
XX
/2
6
, and f
XX
/2
7
are clocks supplied to
peripheral hardware. f
XX
/2
N
is stopped in HALT mode.
Remarks
1. N
: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
(N = 0 to 4)
2. f
XX
: Main system clock frequency (f
X
or f
X
/2)
3. f
X
: Main system clock oscillation frequency
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
5. Figures in parentheses apply to operation with f
X
= 5.0 MHz.
0
0
0
0
0
0
SCS1 SCS0
7
6
5
4
3
2
1
0
Symbol
SCS
FF47H
00H
R/W
Address
After Reset
R/W
SCS1 SCS0
0
0
0
1
1
0
1
1
INTP0 Sampling Clock Selection
MCS = 1
MCS = 0
f
XX
/2
N
f
X
/2
7
(39.1 kHz)
f
XX
/2
7
f
X
/2
8
(19.5 kHz)
f
X
/2
5
(156.3 kHz)
f
XX
/2
5
f
X
/2
6
(78.1 kHz)
f
X
/2
6
(78.1 kHz)
f
XX
/2
6
f
X
/2
7
(39.1 kHz)