NEC uPD78P078 - Manual (Page 260)

260
CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Table 10-4. 8-Bit Timer/Event Counters 5 and 6 Interval Times
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0 0 0 0 TIn input cycle 2 8 x TIn input cycle TIn input edge input cycle
0 0 0 1 TIn input cycle 2 8 x TIn input cycle TIn input edge input cycle
(Setting prohibited) 1/f
X (Setting prohibited) 2 8 x 1/f
X (Setting prohibited) 2 x 1/f
X
(200 ns) (51.2
µ
s) (200 ns)
1/f
X
2 x 1/f
X
2 8 x 1/f
X
2 9 x 1/f
X
1/f
X
2 x 1/f
X
(200 ns) (400 ns) (51.2
µ
s) (102.4
µ
s) (200 ns) (400 ns)
2 x 1/f X 2 2 x 1/f X 2 9 x 1/f X 2 10 x 1/f X 2 x 1/f X 2 2 x 1/f X
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
2 2 x 1/f X 2 3 x 1/f X 2 10 x 1/f X 2 11 x 1/f X 2 2 x 1/f X 2 3 x 1/f X
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
2 3 x 1/f X 2 4 x 1/f X 2 11 x 1/f X 2 12 x 1/f X 2 3 x 1/f X 2 4 x 1/f X
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
2 4 x 1/f X 2 5 x 1/f X 2 12 x 1/f X 2 13 x 1/f X 2 4 x 1/f X 2 5 x 1/f X
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
2 5 x 1/f X 2 6 x 1/f X 2 13 x 1/f X 2 14 x 1/f X 2 5 x 1/f X 2 6 x 1/f X
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
2 6 x 1/f X 2 7 x 1/f X 2 14 x 1/f X 2 15 x 1/f X 2 6 x 1/f X 2 7 x 1/f X
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
2 7 x 1/f
X
2 8 x 1/f
X
2 15 x 1/f
X
2 16 x 1/f
X
2 7 x 1/f
X
2 8 x 1/f
X
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
2 8 x 1/f
X
2 9 x 1/f
X
2 16 x 1/f
X
2 17 x 1/f
X
2 8 x 1/f
X
2 9 x 1/f
X
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
2 9 x 1/f
X
2 10 x 1/f
X
2 17 x 1/f
X
2 18 x 1/f
X
2 9 x 1/f
X
2 10 x 1/f
X
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
2 11 x 1/f X 2 12 x 1/f X 2 19 x 1/f X 2 20 x 1/f X 2 11 x 1/f X 2 12 x 1/f X
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Other than above Setting prohibited
Remarks 1. f X : Main system clock oscillation frequency
2. MCS : Bit 0 of oscillation mode selection register (OSMS)
3. TCLn0 to TCLn3 : Bits 0 to 3 of timer clock select register n (TCLn)
4. Figures in parentheses apply to operation with f
X
= 5.0 MHz.
5. n = 5, 6
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
TCLn3 TCLn2 TCLn1 TCLn0