Sundance Spas ST201 - Manual (Page 65)

65
Sundance Technology ST201 PRELIMINARY draft 2
INTSTATUS
Class....................I/O Registers, Interrupt
Base Address ......IoBaseAddress register value
Address Offset .....0x4e
Access Mode .......Read/Write
Width ...................16 bits
IntStatus register indicates the source of interrupts and indications on the ST201. Bits 1 through 10 are the
interrupt-causing sources for the ST201. These bits can be individually disabled as interrupt sources using
the IntEnable register. The host can acknowledge the interrupt by writing a “1” into the indication bit(s),
which will cause ST201 to clear the interrupt indication. IntStatus is cleared by reset.
BIT BIT NAME BIT DESCRIPTION
0 InterruptStatus Asserted when the ST201 is driving the bus interrupt signal. It is a logi-
cal OR of all the interrupt-causing bits after they have been filtered
through the IntEnable register.
1 HostError This bit is set when a catastrophic error related to the bus interface
occurs. The errors which set HostError are: PCI target abort and PCI
master abort. HostError is cleared by GlobalReset/DMA bits set.
2 TxComplete This bit is asserted when a frame whose TxIndicate bit is set has been
successfully transmitted or for any frame that experiences a transmis-
sion error. This interrupt is acknowledged by writing to TxStatus to
advance the status queue.
3 MACControlFrame This bit is set when a MAC Control frame has been received by the
ST201. MACControlFrame is acknowledged by writing a 1 to this bit.
4 RxComplete This bit is set when one or more entire frames have been received into
the RxFIFO. This bit is automatically acknowledged by the RxDMA
Logic as it transfers frames. Drivers should disable this interrupt and
mask this bit when reading IntStatus.
5 RxEarly This bit is set when the number of bytes of the top frame that have
been received is greater than the value of RxEarlyThresh. When the
top frame has been completely received by the ST201, RxEarly will be
negated and RxComplete will assert. RxEarly is acknowledged by writ-
ing a 1 to this bit.
6 IntRequested This bit is set when the host requested interrupt by setting InterruptRe-
quest bit or by the expiration of the Countdown. It is acknowledged by
writing a 1 to this bit.
7 UpdateStats This bit indicates that one or more of the statistics counters is nearing
overflow condition (typically half of its maximum value). A driver should
respond to an UpdateStats interrupt by reading all of the statistics,
thereby acknowledging and clearing UpdateStats bit.
8 LinkEvent This bit indicates transition of link status of the PHY. This bit can be
acknowledged by writing a 1 into this bit.