Sundance Spas ST201 - Manual (Page 59)

59
Sundance Technology ST201 PRELIMINARY draft 2
FIFOCTRL
Class....................I/O Registers, FIFO Control
Base Address ......IoBaseAddress register value
Address Offset .....0x3a
Access Mode .......Read/Write
Width ...................16 bits
The bits in this register provide various control and indications of TxFIFO and RxFIFO diagnostic.
BIT BIT NAME BIT DESCRIPTION
0 RAMTestMode When set, the FIFO RAM is in the test mode. This bit is cleared after
reset.
8..1 Reserved Reserved for future use. Should be set to 0.
9 RxOverrunFrame This read/write bit determines how the ST201 handles receive overrun
frames. The default is zero, which causes the ST201 to discard all
overrun frames. Setting this bit causes the ST201 to keep and make
visible all overrun frames that have been made visible to the host, so
that they may be inspected for diagnostic purposes.
10 Reserved Reserved for future use. Should be set to 0.
11 RxFIFOFull This read-only bit is set when the RxFIFO is full. This bit does not in
itself indicate an overrun condition. However, if more data is received
while this bit is set, an overrun will occur. This bit is informational in
nature only. This bit is cleared as soon as the RxFIFO is no longer full.
13..12 Reserved Reserved for future use. Should be set to 0.
14 Transmitting Transmitting is read-only and set by ST201 whenever the MAC is
transmitting or waiting to transmit (deferring).
15 Receiving This read-only bit is set whenever the ST201 is receiving a frame into
the RxFIFO. No particular action is expected on the part of the host
based on the state of this bit.