HP E1459A - Manual (Page 87)

86 HP E1459A Register Definitions
Command Register
Port 1/3
The Command Register for Port 1/3 (base + 20
h
) can be read or written. It
contains three bits used to control operating characteristics of the port. If bit
4 of the Control/Status Register is low ("0"), Port 1 data is accessed. If bit
4 is high ("1"), Port 3 data will be accessed. The operation of these
Command Registers is identical to those of Port 0/2.
Command Register Port 1/3 (base + 20h)
For reading and writing, when BS = 0 in the Status/Control Register, the data
for Port 1 is accessed. When BS = 1, the data for Port 3 is accessed.
EDGE ENAB = "1" allows an edge interrupt (INTR for Port 1/3 to cause an
interrupt, if enabled in the Status/Control Register. When "0" edge interrupts
from Port 1/3 are disabled.
INT/EXT = "0" data will be latched using the internal clock. "1" data is
latched using EXT1/3 input.
DAV ENAB = "1" allows the DAV1/3 line to cause an interrupt if enabled
in the Status register. The DAV line is asserted when data is latched. This
15 000F
h
30.5 Hz 32.8 mS 131 - 148 mS
16 0010 h 15.3 Hz 65.5 mS 262 - 294 mS
17 0011 h 7.63 Hz 131 mS 524 - 59 mS
18 0012 h 3.82 Hz 262 mS 1.05 - 1.16 S
19 0013
h
1.91 Hz 524 mS 2.1 - 2.36 S
20 0014
h
0.954 Hz 1.05 S 4.2 - 4.72 S
21 0015
h
0.477 Hz 2.1 S 8.39 - 9.43 S
22 0016
h
0.238 Hz 4.2 S 16.8 - 18.9 S
23 0017
h
0.119 Hz 8.39 S 33.6 - 37.8 S
24 0018
h
60.0 mHz 16.8 S 67.1 - 75 S
25 0019
h
30.0 mHz 33.6 S 134 - 150 S
26 001A
h
15.0 mHz 67.1 S 268 - 300 S
27 001B
h
7.5 mHz 134 S 537 - 600 S
28 001C
h
3.7 mHz 268 S 1074 - 1200 S
29 001D
h
1.9 mHz 537 S 2147 - 2400 S
30 001E h 931 mHz 1074 S 4295 - 4800 S
31 001F h 465.5
µ
Hz 2148 S 8590 - 9600 S
Register Value Bit pattern (hex) Clock Frequency Clock Period Debounce Time
(4 - 4.5 clock periods)
b + 20
h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write No Effect DAV ENAB INT/EXT EDGE ENAB
Read Always Returns FFF h 1 DAV ENAB INT/EXT EDGE ENAB
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