Avago Technologies LSI53C180 - Manual (Page 9)

Contents ix
3.11 Output Current as a Function of Output Voltage 3-15
3.12 Clock Timing 3-16
3.13 Input/Output Timing - Single Transition 3-17
3.14 Input/Output Timing - Double Transition 3-18
3.15 192-Pin PBGA (IJ, I2) Mechanical Drawing 3-20
A.1 LSI53C180 Wiring Diagram 1 of 4 A-2
A.2 LSI53C180 Wiring Diagram 2 of 4 A-3
A.3 LSI53C180 Wiring Diagram 3 of 4 A-4
A.4 LSI53C180 Wiring Diagram 4 of 4 A-5
Tables
1.1 Types of Operation 1-2
1.2 SCSI Bus Distance Requirements 1-4
1.3 Transmission Mode Distance Requirements 1-4
2.1 DIFFSENS Voltage Levels 2-5
2.2 Mode Sense Control Voltage Levels 2-11
2.3 RESET/ Control Signal Polarity 2-12
2.4 WS_ENABLE Signal Polarity 2-12
2.5 XFER_ACTIVE Signal Polarity 2-13
3.1 SCSI A Side Interface Pins 3-5
3.2 SCSI B Side Interface Pins 3-6
3.3 Chip Interface Control Pins 3-6
3.4 Power and Ground Pins 3-7
3.5 Absolute Maximum Stress Ratings 3-8
3.6 Operating Conditions 3-8
3.7 LVD Driver SCSI Signals—B_SD[15:0]
±
, B_SDP[1:0]
±
,
B_SCD
±
, B_SIO
±
, B_SMSG
±
, B_SREQ
±
, B_SACK
±
,
B_SBSY
±
, B_SATN
±
, B_SSEL
±
, B_SRST
±
3-9
3.8 LVD Receiver SCSI Signals—B_SD[15:0]
±
, B_SDP[1:0]
±
,
B_SCD
±
, B_SIO
±
, B_SMSG
±
, B_SREQ
±
, B_SACK
±
,
B_SBSY
±
, B_SATN
±
, B_SSEL
±
, B_SRST
±
3-9
3.9 DIFFSENS SCSI Signal 3-10
3.10 Input Capacitance 3-10
3.11 Bidirectional SCSI Signals—A_SD[15:0]/, A_SDP[1:0]/,
A_SREQ/, A_SACK/, B_SD[15:0]
±
, B_SDP[1:0]
±
,
B_SREQ
±
, B_SACK
±
3-11