Avago Technologies LSI53C180 - Manual (Page 26)

2-8 Functional Descriptions
1. The input signal is blocked if it is being driven by the LSI53C180.
2. The next stage is a leading edge filter. This ensures that the output
does not switch for a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3. A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
2.1.7.4 Busy Control (SBSY)
A_SBSY and B_SBSY signals are propagated from the source bus to the
load bus. The busy control signals go through this process:
1. The bus is tested to ensure the signal if being driven by the
LSI53C180 is not misinterpreted as an incoming signal.
2. The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The input signal
controls the duration.
3. The signal path switches the long and short filters used in the circuit
depending upon the current state of the LSI53C180. The current
state of the LSI53C180 State Machine that tracks SCSI phases
selects the mode. The short filter mode passes data through, while
the long filter mode indicates the bus free state. When the Busy
(SBSY) and Select (SSEL) sources switch from side to side, the long
filter mode is used. This output is then fed to the output driver, which
is a pull-down open collector only.
4. A parallel function ensures that bus (transmission line) recovery is
available for a specified time after the last signal deassertion on each
signal line.
2.1.7.5 Reset Control (SRST)
A_SRST and B_SRST are also passed from the source to the load bus.
This output has pull-down control for an open collector driver. The reset
signals are processed in this sequence:
1. The input signal is blocked if it is already being driven by the
LSI53C180.