2 retiming logic, 3 precision delay control, 4 state machine control – Avago Technologies LSI53C180 User Manual
Page 22: Retiming logic, Precision delay control, State machine control

2-4
Functional Descriptions
LVD Link lowers the amplitude of noise reflections and allows higher
transmission frequencies.
The LVD Link transceivers in Side A and Side B operate in the LVD or
SE modes. The LSI53C180 automatically detects the type of signal
connected, based on the voltages detected by A_DIFFSENS and
B_DIFFSENS.
2.1.2 Retiming Logic
The SCSI signals, as they propagate from one side of the LSI53C180 to
the other side, are processed by logic circuits that retime the bus signals,
as needed, to guarantee or improve the required SCSI timings. The
retiming logic is governed by the State Machine Controls that keep track
of SCSI phases, the location of initiator and target devices, and various
timing functions. In addition, the retiming logic contains numerous delay
elements that are periodically calibrated by the Precision Delay Control
block in order to guarantee specified timing such as output pulse widths,
setup and hold times, and other elements.
When a synchronous negotiation takes place between devices, a nexus
is formed, and the corresponding information on that nexus is stored in
the on-chip RAM. This information remains in place until a chip reset,
power down, or renegotiation occurs. This enables the chip to make
more accurate retiming adjustments.
2.1.3 Precision Delay Control
The Precision Delay Control block provides calibration information to the
precision delay elements in the Retiming Logic block. This calibration
information provides precise timing as signals propagate through the
device. As the LSI53C180 voltage and temperature vary over time, the
Precision Delay Control block periodically updates the delay settings in
the Retiming Logic. The purpose of these updates is to maintain constant
and precise control over bus timing.
2.1.4 State Machine Control
The State Machine Control tracks the SCSI bus phase protocol and other
internal operating conditions. This block provides signals to the Retiming
Logic that identify how to properly handle SCSI bus signal retiming based
on SCSI protocol.