Avago Technologies LSI53C180 - Manual (Page 69)

LSI53C180 Ultra3 SCSI Bus Expander IX-1
Index
Numerics
192-pin plastic ball grid array 1-6
3-state 2-7
leakage 3-11
A
A_SACK 2-9
,
3-5
A_SATN 2-10
,
3-5
A_SBSY 2-8
,
3-5
A_SCD 2-10
,
3-5
A_SD[15:0] 2-6
,
3-5
A_SDP[1:0] 2-6
,
3-5
A_SIO 2-10
,
3-5
A_SMSG 2-10
,
3-5
A_SREQ 2-9
,
3-5
A_SRST 2-8
A_SSEL 2-7
absolute maximum stress ratings 3-8
AC characteristics 3-17
to
3-19
acknowledge
ACK 2-9
,
B-1
active negation 2-3
ANSI B-1
applications 1-3
arbitration B-1
asserted B-1
assertion B-1
asynchronous transmission B-1
ATN B-1
attention (SATN) 2-10
B
B_SACK 2-9
,
3-6
B_SATN 2-10
B_SBSY 2-8
,
3-6
B_SCD 2-10
,
3-6
B_SD[15:0] 2-6
,
3-6
B_SDP[1:0] 2-6
,
3-6
B_SIO 2-10
,
3-6
B_SMSG 2-10
,
3-6
B_SREQ 2-9
B_SRST 2-8
B_SSEL 2-7
,
3-6
backward compatibility 1-7
balanced duty cycles 2-3
bidirectional
connections 2-2
bidirectional SCSI signals 3-11
block B-1
BSY B-1
BSY_LED 2-7
bus B-1
expander B-1
timing 2-4
busy
(BSY) 2-8
filters 2-15
C
C_D B-2
cable skew delay B-2
calibration 2-4
chip reset (RESET/) 2-11
clock
(CLOCK) 2-13
signal 2-7
timing 3-17
connect B-2
control signals B-2
input 3-12
output 3-12
control/data (SCD) 2-10
controller B-2
cyclic redundancy check 1-6
D
data 2-3
,
2-6
path 2-14
DB[7:0] B-2
DC characteristics 3-8
to
3-12
deasserted B-2
delay line structures 2-14
delay settings 2-4
device B-2
differential B-2
transceivers 1-8
DIFFSENS 2-4
,
2-5
receiver 2-5
SCSI signal 3-10
disconnect B-2
distance requirements 1-3
to
1-4
domain validation 1-7
double clocking of data 2-3
double transition clocking 1-6
driver B-2