Avago Technologies LSI53C180 - Manual (Page 71)

Index IX-3
definition B-5
latch 2-7
reconnect
definition B-5
recovery 2-10
release
definition B-5
reliability issue 2-3
REQ B-5
REQ/ACK input signals 2-15
request 2-3
(REQ) 2-9
reselect B-5
reset control 2-8
RESET/ signal 2-11
to
2-12
,
B-5
retiming 2-9
logic 2-1
,
2-4
RST B-5
S
SACK 2-9
SCAM B-5
SCSI
A side interface pins 3-5
Address B-5
B side interface pins 3-6
bidirectional
signals 3-11
bus distance requirements 1-4
bus free state 2-12
bus protocol 2-4
definition B-5
device ID B-5
DIFFSENS signal 3-10
I/O logic 2-10
ID B-5
input filtering 3-15
interface timings 3-17
to
3-19
parallel interconnect 3 1-6
phases 2-4
termination 2-13
TolerANT technology 2-3
SEL B-5
select (SSEL) 2-7
self-calibration 2-14
server clustering 1-3
signal
descriptions 3-1
groupings 2-6
,
3-1
skew 2-2
signal descriptions 2-1
to
2-13
single transition
timing diagram 3-18
single-ended configuration
definition B-6
source bus 2-2
,
2-6
SREQ 2-9
SSEL 2-7
state machine 2-9
control 2-1
,
2-4
storage temperature 3-8
supply voltage 3-8
synchronous transmission
definition B-6
T
target
definition B-6
termination
definition B-6
test conditions
rise/fall time 3-14
thermal resistance 3-8
TolerANT
drivers and receivers 2-3
electrical characteristics 3-13
to
3-14
receiver technology 2-3
SCSI 2-3
technology 2-3
benefits 2-3
transfer active 2-12
to
2-13
transmission mode distance requirements 1-4
U
Ultra3 SCSI 1-6
definition B-6
V
VDD_CORE 3-7
VDD_SCSI 3-7
W
Wide Ultra3 SCSI 2-2
WS_ENABLE 2-12
warm swap enable 2-12
X
XFER_ACTIVE
signal polarity 2-13