Avago Technologies LSI53C180 - Manual (Page 27)

Interface Signal Descriptions 2-9
2. The next stage is a leading edge filter. This ensures that the output
will not switch during a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3. A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
When the LSI53C180 senses a true mode change on either bus, it
generates a SCSI reset to the opposite bus. For example, when LVD
mode changes to SE mode, a reset occurs.
2.1.7.6 Request and Acknowledge Control (SREQ and SACK)
A_SREQ, A_SACK, B_SREQ, and B_SACK are clock and control
signals. Their signal paths contain controls to guarantee minimum pulse
widths, filter edges, and do some retiming when used as data transfer
clocks. In DT clocking, both leading and trailing edges are filtered, while
only the leading edge is filtered in single transition clocking. SREQ and
SACK have paths from the A Side to the B Side and from the B Side to
the A Side. The received signal goes through these processing steps
before being sent to the opposite bus:
1. The asserted input signal is sensed and forwarded to the next stage
if the direction control permits it. The direction controls are developed
from state machines that are driven by the sequence of bus control
signals.
2. The signal must then pass the test of not being regenerated by the
LSI53C180.
3. The next stage is a leading edge filter. This ensures that the output
does not switch during the specified hold time after the leading edge.
The duration of the input signal determines the duration of the output
after the hold time. The circuit guarantees a minimum pulse rate.
4. The next stage passes the signal if it is not a data clock. If SREQ or
SACK is a data clock, it delays the leading edge to improve data
output setup times. The input signal again controls the duration.
5. This stage is a trailing edge signal filter. When the signal deasserts,
the filter does not permit any signal bounce. The output signal
deasserts at the first deasserted edge of the input signal.