Avago Technologies LSI53C180 - Manual (Page 52)

3-18 Specifications
Figure 3.13 Input/Output Timing - Single Transition
Table 3.18 Output Timing - Single Transition
Symbol Parameter Min Max Units
t
ST5
Output data setup Nominal: negotiated/2 – ns
t
ST6
Output data hold Nominal: negotiated/2 – ns
t
ST7
Output REQ/ACK pulse width max [negotiated ns,
t
ST3
−
5]
max [negotiated ns,
t
ST3
+5]
ns
t
ST8
REQ/ACK transport delay 25 ns if REQ/ACK is
clock for input data,
10 ns if not 50 ns if REQ/ACK is
clock for input data,
30 ns if not ns
Note: Pulse width is a negotiated value and ranges from 12.5 to over 1000 ns.
Table 3.19 Input Timing - Double Transition
Symbol Parameter Min Max Units
t
DT1
Input data setup 1.25 – ns
t
DT2
Input data hold 1.25 – ns
t
DT3
Input REQ/ACK assertion pulse width 10 – ns
t
DT4
Input REQ/ACK deassertion pulse width 10 – ns
t
ST3
SREQ/SACK
Receive Data
(SD[15:0]/)
t
ST4
t
ST1
t
ST2
Send Data
(SD[15:0]/
Output
t
ST8
t
ST5
t
ST7
t
ST6
REQ/ACK