Avago Technologies LSI53C180 - Manual (Page 40)

3-6 Specifications
Table 3.2 SCSI B Side Interface Pins
SCSI B Pin Type Description
B_SSEL+,
−
H2, J1 I/O B Side SCSI bus Select control signal.
B_SBSY+,
−
M3, N1 I/O B Side SCSI bus Busy control signal.
B_SRST+,
−
K2, L1 I/O B Side SCSI bus Reset control signal.
B_SREQ+,
−
G1, G2 I/O B Side SCSI bus Request control signal.
B_SACK+,
−
M1, M2 I/O B Side SCSI bus Acknowledge control signal.
B_SMSG+,
−
J2, K1 I/O B Side SCSI bus Message control signal.
B_SCD+,
−
H3, H1 I/O B Side SCSI bus Control and Data control signal.
B_SIO+,
−
F1, F2 I/O B Side SCSI bus Input and Output control signal.
B_SATN+,
−
N2, P1 I/O B Side SCSI bus Attention control signal.
B_SDP[1:0]+,
−
T9, U9, P3, P2 I/O B Side SCSI bus Data Parity signal.
B_SD[15:0]+,
−
T10, U10, T11, U11,
T12, U12, T13, U13,
B1, B2, C1, C2,
D1, D2, E1, E2,
R2, R3, T2, U2,
T3, U3, T4, U4,
T5, U5, R6, T6,
T7, U7, T8, R8 I/O B Side SCSI bus Data signals.
B_DIFFSENS C3 I B Side SCSI bus Differential Sense signal.
B_RBIAS R1 RBIAS LVD current control.
Table 3.3 Chip Interface Control Pins
Control Pin Type Description
RESET/ A7 I Master Reset for LSI53C180, active LOW.
WS_ENABLE/ B5 I Enable/disable SCSI transfers through the LSI53C180.
XFER_ACTIVE A6 O Transfers through the LSI53C180 are enabled/disabled.
CLOCK C8 I Oscillator input for LSI53C180 (40 MHz).
BSY_LED B6 O SCSI activity LED output, 8 mA.