Avago Technologies LSI53C180 - Manual (Page 33)

Internal Control Descriptions 2-15
2.2.2.2 REQ/ACK
These input clock signals get edge filtered and stretched to minimum
values to avoid glitches. In DT clocking, both leading and trailing edges
are filtered, while only the leading edge is filtered in single transition
clocking. These filters provide edge filtering to remove noise within the
initial signal transition. The current transmission speed selects the time
values.
2.2.3 Busy Filters
The busy control signal passes from source to load bus with filtering
selected by the current state of the SCSI bus. This filter provides a
synchronized leading edge signal that is not true until the input signal has
been stable. The trailing edge occurs within several nanoseconds of the
input being deasserted. When the BSY signal is asserted before and
after the SEL signal, the filter is on.