Avago Technologies LSI53C180 - Manual (Page 53)

Electrical Characteristics 3-19
Figure 3.14 Input/Output Timing - Double Transition
Table 3.20 Output Timing - Double Transition
Symbol Parameter Min Max Units
t
DT5
Output data setup Nominal: negotiated/2 – ns
t
DT6
Output data hold Nominal: negotiated/2 – ns
t
DT7
Output REQ/ACK pulse width max [negotiated ns,
t
DT3
−
5]
max [negotiated ns,
t
DT3
+5]
ns
t
DT8
REQ/ACK transport delay 25 ns if REQ/ACK is
clock for input data,
10 ns if not 50 ns if REQ/ACK is
clock for input data,
30 ns if not ns
Note: Pulse width is a negotiated value and ranges from 12.5 to over 1000 ns.
t
DT3
SREQ/SACK
Receive Data
(SD[15:0]/)
t
DT4
t
DT1
t
DT2
t
DT1
t
DT2
Send Data
(SD[15:0]/)
Output
t
DT5 t
DT6
t
DT8
t
DT7
REQ/ACK