Avago Technologies LSI53C180 - Manual (Page 36)

3-2 Specifications
Figure 3.1 Left Half of LSI53C180 192-Pin BGA Top View
A1 A2 A3 A4 A5 A6 A7 A8 A9
NC VDD IO NC NC NC XFER_ACTIVE RESET/ A_DIFFSENS A_SD12-
B1 B2 B3 B4 B5 B6 B7 B8 B9
B_SD11+ B_SD11- NC NC WS_ENABLE/ BSY_LED NC VDD CORE A_SD12+
C1 C2 C3 C4 C5 C6 C7 C8 C9
B_SD10+ B_SD10- B_DIFFSENS NC VDD SCSI NC VSS CLOCK VDD SCSI
D1 D2 D3
B_SD9+ B_SD9- NC
E1 E2 E3
B_SD8+ B_SD8- VDD SCSI
F1 F2 F3
B_SIO+ B_SIO- NC
G1 G2 G3 G7 G8 G9
B_SREQ+ B_SREQ- VSS VSS VSS VSS
H1 H2 H3 H7 H8 H9
B_SCD- B_SSEL+ B_SCD+ VSS VSS VSS
J1 J2 J3 J7 J8
B_SSEL- B_SMSG+ VDD SCSI VSS VSS
K1 K2 K3 K7 K8 K9
B_SMSG- B_SRST+ VDD CORE VSS VSS VSS
L1 L2 L3 L7 L8 L9
B_SRST- NC VSS VSS VSS VSS
M1 M2 M3
B_SACK+ B_SACK- B_SBSY+
N1 N2 N3
B_SBSY- B_SATN+ VDD SCSI
P1 P2 P3
B_SATN- B_SDP0- B_SDP0+
R1 R2 R3 R4 R5 R6 R7 R8 R9
B_RBIAS B_SD7+ B_SD7- NC VDD SCSI B_SD2+ VSS B_SD0- VDD SCSI
T1 T2 T3 T4 T5 T6 T7 T8 T9
NC B_SD6+ B_SD5+ B_SD4+ B_SD3+ B_SD2- B_SD1+ B_SD0+ B_SDP1+
U1 U2 U3 U4 U5 U6 U7 U8 U9
NC B_SD6- B_SD5- B_SD4- B_SD3- NC B_SD1- VDD CORE B_SDP1-