Artesyn MOTLoad Firmware Package User's Manual (February 2015) - Manual (Page 257)

Remote Start
MOTLoad Firmware Package User’s Manual (6806800C24D) 257
The target processor will receive an interrupt each time the target's IBCA is written by the host.
Although it is most efficient if the host writes the entire command word in a single VME write,
it is acceptable to build a command in incremental fashion, as long as the OWN bit is cleared in
the very last write. The target will process the command when the OWN bit is cleared; no other
action is required by the host.
The VMEbus address of the VME Bridge mailbox register is controlled by the VME configuration
of the board. This is documented in the board's Installation and Use Manual.
If the VME Bridge converts from PCI to VME, then the IBCA will be viewed in a byte-swapped
order from the processor. Therefore, the bit orders shown in this chapter will need to be byte-
swapped when viewed directly using MOTLoad. For instance, the IBCA after reset is said to
contain the "RST" flag as, 0x80525354. However, when viewed from the processor's
perspective using MOTLoad's mdw command, the "RST" flag is: 0x54535280. See
Demonstration of the Host Interface on page 258 , below, for detailed examples of this.
B.2.12 CompactPCI Remote Start
Remote Start in a CompactPCI chassis adheres to the protocol defined throughout this chapter.
The Intel 2155x PCI-to-PCI bridge device Scratch 7 register is used as the Inter-Board
Communication Address (IBCA). The Intel 2155x Secondary Doorbell 0 is used to notify the
target of a command to be processed.
PCI interrupts are not generated onto the Compact PCI backplane by the Remote Start feature.
The host should poll the IBCA OWN bit to determine if a command has completed.
The PCI address of the PCI-to-PCI Bridge Scratch7 and Doorbell register is controlled by the PCI
configuration of the board.
Issuing a Remote Start command is a three step process. In the first step, the host ensures the
OWN bit is set in the IBCA. In the second step, the 32-bit command opcode is written by the
host to the IBCA. In the third step, the host notifies the target that a command is waiting by
writing a 16- bit value, with the Secondary Doorbell 0 bit set, to the Secondary Interrupt
Request register. The target will respond to the doorbell interrupt, clear the Doorbell 0 request,
and set the OWN bit in the IBCA. The host should poll the OWN bit, and ensure it is set, prior to
writing another opcode.