Altera Nios Development Board - Manual (Page 45)

Altera Corporation A–1
July 2005
Appendix A. Shared Bus Table
Description On the Nios development board, Stratix II edition, the flash memory,
SRAM and Ethernet MAC/PHY devices share address and control lines.
These shared lines are referred to as the Shared Bus. Using SOPC Builder,
designers can interface a Nios II processor system to any device
connected to the off-chip Shared Bus.
Table A–9 on page A–1 lists all
connections between the devices connected to the Shared Bus.
Table A–9. Shared Bus Table (Part 1 of 3)
NET Name
NET
Description
PLD (U60) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4)
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
FSE_A0 Shared
Address IO T2 D15/A-1 51
FSE_A1 IO T3 A0 31 A1 78
FSE_A2 IO U1 A1 26 A0 1 A0 1 A2 79
FSE_A3 IO U2 A2 25 A1 2 A1 2 A3 80
FSE_A4 IO V1 A3 24 A2 3 A2 3 A4 81
FSE_A5 IO V2 A4 23 A3 4 A3 4 A5 82
FSE_A6 IO W1 A5 22 A4 5 A4 5 A6 83
FSE_A7 IO W2 A6 21 A5 18 A5 18 A7 84
FSE_A8 IO Y1 A7 20 A6 19 A6 19 A8 85
FSE_A9 IO Y2 A8 10 A7 20 A7 20 A9 86
FSE_A10 IO AA1 A9 9 A8 21 A8 21 A10 87
FSE_A11 IO AA2 A10 8 A9 22 A9 22 A11 88
FSE_A12 IO AB1 A11 7 A10 23 A10 23 A12 89
FSE_A13 IO AB2 A12 6 A11 24 A11 24 A13 90
FSE_A14 IO W3 A13 5 A12 25 A12 25 A14 91
FSE_A15 IO W4 A14 4 A13 26 A13 26 A15 92
FSE_A16 IO Y3 A15 3 A14 27 A14 27
FSE_A17 IO Y4 A16 54 A15 42 A15 42
FSE_A18 IO AA3 A17 19 A16 43 A16 43
FSE_A19 IO AA4 A18 18 A17 44 A17 44
FSE_A20 IO AB3 A19 11
FSE_A21 IO AB4 A20 12
FSE_A22 IO AC2 A21 15
FSE_A23 IO AC3 A22 2
FSE_A24 IO P5 NC.A23 (1) 1