Altera Nios Development Board User Manual
Page 29
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Altera Corporation
2–21
July 2005
Nios Development Board Reference Manual, Stratix II Edition
Board Components
provides CompactFlash pin out details.
Table 2–6. CompactFlash (CON3) Pin Table (Part 1 of 2)
Pin on
CompactFlash
(CON3)
CompactFlash
Function (U60)
Connects to
(1)
1
GND
GND
2
D03
H9
3
D04
C5
4
D05
C4
5
D06
F8
6
D07
E8
7
-CE
A9
8
A10
H11
9
-OE
W16
10
A09
A10
11
A08
E7
12
A07
B3
13
VCC
Y17
(
2)
14
A06
B4
15
A05
E9
16
A04
C6
17
A03
B6
18
A02
C8
19
A01
D9
20
A00
D8
21
D00
H10
22
D01
D6
23
D02
A5
24
WP
F11
25
-CD2
GND
(3)
26
-CD1
AB16
27
D11
K10
28
D12
G9
29
D13
B5
30
D14
A6
31
D15
K11
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)