Altera Nios Development Board User Manual
Page 30
2–22
Altera
Corporation
Nios Development Board Reference Manual, Stratix II Edition
July 2005
CompactFlash Connector (CON3)
f
For more information on the CompactFlash connector (CON3), refer to
www.compactflash.org
and www.molex.com.
32
-CE2
Y16
33
-VS1
GND
(3)
34
-OIORD
C7
35
-IOWR
A7
36
-WE
E10
37
RDY/BSY
J11
38
VCC
Y17
(
2)
39
-CSEL
GND
(3)
40
-VS2
no connect
(3)
41
RESET
(4)
42
-WAIT
D7
43
-INPACK
B7
44
-REG
B8
45
BVD2
G11
46
BVD1
C11
47
D081
J9
48
D091
A3
49
D101
C3
50
GND
GND
(3)
Note to
(1)
All pin numbers represent I/O pins on the FPGA, unless
otherwise noted.
(2)
This FPGA I/O pin controls a power MOSFET that supplies 5V
VCC to CON3.
(3)
This pin does not connect to the FPGA directly.
(4)
RESET is driven by the EPM7128AE configuration controller
device.
Table 2–6. CompactFlash (CON3) Pin Table (Part 2 of 2)
Pin on
CompactFlash
(CON3)
CompactFlash
Function (U60)
Connects to
(1)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)