Altera Nios Development Board - Manual (Page 25)

Altera Corporation 2–17
July 2005 Nios Development Board Reference Manual, Stratix II Edition
Board Components
Figure 2–8. PROTO1 Pin Information - J11, J12 & J13
Note to Figure 2–8
(1) Unregulated voltage from DC power supply
(2) Clk from board oscillator
(3) Clk from FPGA via buffer
(4) Clk output from protocard to FPGA
RESET_n
E8 F8 C4 C5 H9 A5 D6
H10
GND
F10
A7 C7 D7
G10
J11
D9 D8 A9
G11
GND J9 A3 C3 K10 G9 B5 A6 K11 NC GND GND GND A8 GND F11 NC C8 E11 GND
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
J12
J11
(1)
Vu
nreg (U
5
4 pin 2)
N
C
V
C
C
3_3
V
C
C
3_3
(2)
P
RO
TO
1
_O
SC
(U
2 pin 6)
(3)
P
RO
TO
1
_C
LK
IN
(U
2 pin
17)
(4)
P
RO
TO
1
_C
LK
O
U
T (A
C
14)
V
C
C
3_3
V
C
C
3_3
V
C
C
3_3
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
1 3 5 7 9
11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
G
N
D
B8
C
11 E7 B
4
C
6
E
10
V
C
C
5
H
11
A
10
B
3
E9 B6 B7
1 3 5 7 9
11 13
2 4 6 8 10 12 14
J13