Jtag connectors (j24 & j5), Jtag connector to stratix ii device (j24), Jtag connectors (j24 & j5) –31 – Altera Nios Development Board User Manual
Page 39: Figure 2–17
Altera Corporation
2–31
July 2005
Nios Development Board Reference Manual, Stratix II Edition
Board Components
Figure 2–17. Reset, Config Button
JTAG
Connectors (J24
& J5)
The Nios development board, has two 10-pin JTAG headers (J24 and J5)
compatible with Altera download cables, such as the USB-Blaster
™
. Each
JTAG header connects to one Altera device and forms a single-device
JTAG chain. J24 connects to the Stratix II device (U60), and J5 connects to
the EPM7128AE device (U3).
JTAG Connector to Stratix II Device (J24)
J24 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the
Stratix II device (U60) as shown in
. Altera Quartus II
software can directly configure the Stratix II device with a new hardware
image via an Altera download cable as shown in
. In addition,
the Nios II IDE can access the Nios II processor JTAG debug module via
a download cable connected to the J24 JTAG connector.
Figure 2–18. JTAG Connector (J24) to Stratix II Device
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)