Altera Nios Development Board User Manual
Page 24
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2–16
Altera
Corporation
Nios Development Board Reference Manual, Stratix II Edition
July 2005
Expansion Prototype Connectors (PROTO1 & PROTO2)
■
A logic-negative power-on reset signal.
■
Five regulated 3.3V power-supply pins (2A total max load for both
PROTO1 & PROTO2).
■
One regulated 5V power-supply pin (1A total max load for both
PROTO1 & PROTO2).
■
Numerous ground connections.
The PROTO1 expansion prototype connector shares Stratix II I/O pins
with the CompactFlash connector (CON3). Designs may use either the
PROTO1 connector or the CompactFlash connector.
f
Refer to the Altera web site for a list of available expansion daughter
cards that can be used with the Nios development board at
www.altera.com/devkits.
, and
show connections from the
PROTO1 expansion headers to the Stratix II device. Unless otherwise
noted, labels indicate Stratix II device pin numbers.
Figure 2–7. PROTO1 Expansion Prototype Connector - J11, J12 & J13
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)